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ISL58214
TABLE 6. HFMFREQ: HFM FREQUENCY SETTING (REG 0-16)
BIT
B7-B0
BIT
B7-B0
BIT
B7-B0
BIT
B7
B6-B0
BIT
B7
B6-B0
BIT
B7-B4
B3-B0
BIT
B7-B3
B2-B0
BIT
B7 - B0
NAME
HFMFREQ
NAME
HFMON
NAME
THRESHH
NAME
Unlink
Reserved
NAME
REGRST
Reserved
NAME
Reserved
THRESH-L
NAME
Reserved
SDAMP1
NAME
HFMCNT
14
BIT DEFINITION
HFMFREQ = F MIN + F STEP (128B7 +64B6 + 32B5 + 16B4 + 8B3 + 4B2 + 2B1 + B0)
Note: If HFMFREQ = 00h, the HFM output is DC
TABLE 7. HFMON: HFM ON-AMPLITUDE (REG 0-17)
BIT DEFINITION
TABLE 8. THRESHH: THRESHOLD CURRENT HIGH ORDER BITS (REG 0-19)
BIT DEFINITION
THRESH = k(2048B7 +1024B6 + ... + 32B1 + 16B0 + THRESHL) THRESHL bits are in Reg 1-0A
TABLE 9. UNLINK: UNLINK CONTROL (REG 0-21)
BIT DEFINITION
If unlink = 1, the SCALE DAC gets its reference from the ISLOPE pin only.
If unlink = 0, the SCALE DAC gets its reference from the RSET pin and the ISLOPE pin.
Leave 0000000
TABLE 10. CR3: CONTROL REGISTER 3 (REG 1-08)
BIT DEFINITION
Resets all registers.
1: Reset. Safety interlock allows reset bit to have effect only when lower three bits of CR0 are cleared (CE
= OE = WE = 0).
0: Normal operation.
TABLE 11. THRESHL: THRESHOLD CURRENT LOW ORDER BITS (REG 1-09)
BIT DEFINITION
Leave 0000
THRESH-L = k(THRESH-H + 8B3 + 4B2 + 2B1 + B0), THRESH-H is Reg 0-19
TABLE 12. SLOW DAMPING CONTROL (REG 1-0A)
BIT DEFINITION
Leave 0000
I SRC Write Waveform Damping
TABLE 13. HFM FREQUENCY COUNT REGISTER (READ MODE) (REG 1-0E)
BIT DEFINITION
HFM cycles when SEN is high when HFM counting is enabled. B7 is the MSB. The counter will roll-over if
the count exceeds 255.
Reg X-01, bit 7 = 1 enables the HFM counter. Reg 1-0E bit 1 enables the serial HFM counter.
FN6944.1
July 29, 2013
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